College of Computer Science and Technology Nanjing, University of Aeronautics and Astronautics, Nanjing 210016, China.
International Journal of Science and Research Archive, 2025, 17(03), 353-363
Article DOI: 10.30574/ijsra.2025.17.3.3244
Received on 02 November 2025; revised on 09 December 2025; accepted on 11 December 2025
The LoongArch instruction set architecture (ISA) has become a cornerstone in efforts to build a secure, autonomous, and high-performance domestic computing ecosystem. To make Loongson processors practical for real software deployment, a dependable and well-optimized compiler is essential—particularly for emerging 32-bit platforms such as LoongArch32R. This study develops a complete and reproducible workflow for adapting and optimizing the GNU C Compiler (GCC) for LoongArch32R, enabling reliable instruction generation and performance-focused code transformation. The work combines several technical components: validation of the GCC backend, execution through QEMU in both user-level and system-level environments, incorporation of the MOS teaching operating system with custom benchmark applications, detailed examination of LSX SIMD auto-vectorization, and the introduction of a prototype custom vector instruction (VCUBE.W) through assembler-level extension. A structured benchmarking suite—including matrix multiplication, prime sieve, STREAM-like memory workloads, and memory operations—was implemented to evaluate optimization levels and compiler behavior. Performance measurements were analyzed and visualized using Python-based graphing tools. The experimental results show clear runtime improvements from standard optimization flags and demonstrate partial vectorization benefits, verifying that the ported compiler is functional, stable, and capable of generating efficient LoongArch32R code. Overall, the framework produced in this work offers a practical foundation for future compiler development, educational use, and broader software ecosystem support for LoongArch-based systems.
Loongarch; GCC; Compiler Porting; Vectorization; LSX; Loongson; QEMU; Performance Optimization; MOS; Embedded Systems
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Md Shahariar Idris Robin, Shi Huibin and Jannatul Mawa Mahin. C compiler porting and optimization for the 32-Bit Loong Arch CPU. International Journal of Science and Research Archive, 2025, 17(03), 353-363. Article DOI: https://doi.org/10.30574/ijsra.2025.17.3.3244.
Copyright © 2025 Author(s) retain the copyright of this article. This article is published under the terms of the Creative Commons Attribution Liscense 4.0







